Stacked conductive resistive polysilicon lands in multilevel semiconductor chips

摘要

A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick passivating layer is formed of an etch stop layer and a layer of phosphosilicate glass (PSG) above the substrate. A set of first metal contact studs through the first thick passivating layer contacts at least one of the active regions and/or the polysilicon lines. The etch stop layer (26) may be of intrinsic polysilicon or Al2O3. The top surface of the first contact studs is coplanar with the top surface of the first thick passivating layers. A plurality of polysilicon lands formed on the planar structure contact the first contact studs. The polysilicon lands are highly resistive, highly conductive or a mix thereof. A second thick passivating layer is formed above the resulting structure having a set of second metal contact studs therein. The second metal studs contact at least one of the polysilicon lands and/or one of the first contact studs. The top surface of the second contact studs is coplanar with the top surface of the second thick passivating layer. A plurality of metal lands is formed above the second thick passivating layer and in contact with the second contact studs. A final insulating film insulates and passivates the metal lands.