发明名称 |
Apparatus for a bus-based integrated circuit test architecture |
摘要 |
The present invention provides an access mechanism for the testing of modules within an integrated circuit. A test access architecture is implemented which allows embedded testing of reusable modules with reusable test vectors regardless of the configuration of the integrated circuit. Modules within the integrated circuit may receive previously developed test vectors directly from a test input bus without having to propagate them through intervening modules. The module is controlled to accept as input either normal system inputs or the previously developed test vectors by logic circuits embedded within each module. The module's output is routed by a test output bus for dynamically observing test results at the system pins.
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申请公布号 |
US5379308(A) |
申请公布日期 |
1995.01.03 |
申请号 |
US19920870877 |
申请日期 |
1992.04.20 |
申请人 |
INTEL CORPORATION |
发明人 |
NGUYEN, HANG T. T.;RAMAN, SRINIVAS |
分类号 |
G01R31/3185;(IPC1-7):H04B17/00 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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