发明名称 Apparatus and method for managing interrupts in a multiprocessor system
摘要 A system and method for selecting a processor to service interrupts in a multiprocessor system with processor individualized interrupt priority states. The interrupt priority information associated with the various processors is bit serially compared to select one or more processors of lowest interrupt priority status, Processor individualized identification information is then compared to reconcile when multiple processors have an identical interrupt priority level, The outcome is stored and immediately available for managing interrupts generated by I/O devices, In a preferred arrangement, the interrupt priority status of the selected processor is confirmed immediately before processing the service requests to compensate for any changes occurring during the period of the bit serial comparison.
申请公布号 US5379434(A) 申请公布日期 1995.01.03
申请号 US19940258127 申请日期 1994.06.10
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 DIBRINO, MICHAEL T.
分类号 G06F15/16;G06F9/48;G06F13/26;G06F15/177;(IPC1-7):G06F13/26 主分类号 G06F15/16
代理机构 代理人
主权项
地址