Process for manufacturing MOS transistors having planar source and drain regions, short channel length and a self-aligned contact level comprising a metallic silicide.

摘要

The invention relates to a method for producing MOS transistors with flat source/drain zones, short channel lengths, and a self aligned contacting plane comprised of a metal silicide. In this method, the source/drain zones in the semiconductor substrate are produced by out-diffusion of the contacting plane consisting of a doped metal silicide and deposited directly on the substrate. The method serves to produce NMOS, PMOS, and in particular CMOS circuits in VLSI technology and permits a very high packing density and an independent additional wiring plane of very low resistance.