发明名称 |
Image memory device |
摘要 |
An image memory device wherein data necessary for interpolation is read out simply and successively from a frame memory at a time without requiring a complicated timing control circuit to allow interpolation processing to be performed at a high speed. Image data are temporarily stored into a plurality of parallel frame memories having an interleave construction. Conversion addresses for the frame memories are generated based on different conversion rules from a plurality of address decoders and applied in parallel at a time to the frame memories so that data at neighboring points of a coordinate position for an object of interpolation are outputted at a time from the frame memories. The neighboring point data are inputted in parallel at a time, or pipeline inputted, to an interpolation calculation circuit so that coefficients are generated from individual pipelines. Product sum calculation is performed for the coefficients and the neighboring point data.
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申请公布号 |
US5376973(A) |
申请公布日期 |
1994.12.27 |
申请号 |
US19940186129 |
申请日期 |
1994.01.25 |
申请人 |
NEC CORPORATION |
发明人 |
KATAYAMA, YOICHI;HARASAKI, HIDENOBU |
分类号 |
G09G5/36;G06T1/60;G06T3/40;G06T13/00;G06T13/80;H04N5/262;H04N5/907;H04N7/01;(IPC1-7):H04N7/01 |
主分类号 |
G09G5/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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