发明名称 Integrated circuit package for flexible computer system alternative architectures
摘要 A single-packaged central processing unit (CPU) is formed on a substrate for a particular application in a variable word length computer system that includes a program memory. A first semiconductor chip in the CPU is of a general purpose type and includes a plurality of elements interconnected, such as an arithmetic logic unit (ALU), a program counter, and a register. A second semiconductor chip in the CPU is mounted on the first semiconductor chip with their active surfaces facing each other. The second semiconductor chip is configured for the particular application in accordance with a particular program instruction set stored in the program memory. The second semiconductor chip includes a command register for receiving fetched commands from the program memory, a command decoder for decoding the fetched commands and for generating corresponding control signals, and a timing generator for generating system clock signals. In one embodiment, the command register has a particular bit length for adapting to the particular application. In another embodiment, the command decoder has a particular bit length and the timing generator is configured to generate particular corresponding control signals for adapting to the particular application.
申请公布号 US5376825(A) 申请公布日期 1994.12.27
申请号 US19930154151 申请日期 1993.11.18
申请人 SEIKO EPSON CORPORATION 发明人 TUKAMOTO, TAKASHI;ABE, SACHIYUKI;YABUSHITA, TETSUO;HAYASHI, YOSHIMITSU
分类号 G06F9/32;G06F15/78;H01L21/60;H01L23/31;H01L23/492;H01L23/495;H01L23/498;H01L25/065;H01L25/07;H01L25/10;H01L25/18;(IPC1-7):H01L23/02;H01L23/12 主分类号 G06F9/32
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