| 摘要 |
A data communication circuit comprising a slave device (3), a master device (2) and a two-wire bus (6) wherein the master device (2) creates a potential difference (v(t)) between said two wires so as to provide power to said slave device (3). The slave device (3) comprises a pulse decoder (20) for detecting said pulses and producing a synchronisation signal (Clk) upon the detection of each said pulse. The master device (2) also comprises a pulse control circuit (40) for causing the pulse creating circuit to create a series of data pulses having the same state when the digital information is read from the slave device (3). In addition, the slave device (3) further comprises a circuit (43,58) for changing the state of selected ones of data pulses in the series in response to the digital information to be read.
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