| 摘要 |
The circuit provides the ES (errored second) detector which counts the frequency of bit error on the transmission path or line section in the transmission system and detects the continuous time of breakdown. The circuit includes an error bit detector (10) detecting the error bit and generating the data clock simultaneously, a clock generator (20) generating the master clock, a read enable signal generator (30) dividing the master clock and generating the read enable signal/reset signal in the period of 1sec, an ES detector (40) detecting 1 bit of ES signal corresponding to one period of master clock, an ES counter (50) counting the frequency of ES signal with the master clock, and a CPU (60) generating the reset signal of ES counter.
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