发明名称 Sigma-delta analogue/digital converter stabilized by chopping
摘要 A sigma-delta analogue/digital converter stabilized by chopping (ADC) comprises a time-discrete multiplier for receiving an analogue input signal and a first time-discrete sequence, and for multiplying them so as to obtain a chopped analogue signal. A chopping-type sigma-delta ADC is connected in series to the time-discrete multiplier so as to receive and to convert the chopped analogue signal into a digital output signal, the chopping-type sigma-delta ADC being characterised in the z domain by: <IMAGE> where ST'(z) is a transfer function of the signal, and is characterised by a passband in the high-frequency range; and NT'(z) is a noise transfer function, and characterised by high attenuation in the high-frequency range. The low-frequency noise of the circuit may thus be suppressed in order to increase the resolution of the converter. <IMAGE>
申请公布号 FR2706703(A1) 申请公布日期 1994.12.23
申请号 FR19930006925 申请日期 1993.06.09
申请人 NATIONAL SCIENCE COUNCIL 发明人 WU CHUNG-YU;CHANG YING-HWI;YU TSAI-CHUNG
分类号 H03F1/30;H03M3/02;(IPC1-7):H03M3/02;H03M1/08 主分类号 H03F1/30
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