发明名称 MASK PATTERN DESIGNING METHOD AND DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To reduce a length difference in actual wirings to a prescribed value or below so as to lessen a semiconductor integrated circuit in skew by a method wherein a wiring pattern is so converted by processing as to be replaced with another wiring pattern provided with a via-contact. CONSTITUTION:Logic data are inputted at a step S1, and cells are automatically laid out at a step S2. In succession, nets wherein a length difference in actual wirings is required to be reduced to a prescribed value or below are given a wiring starting point and a wiring terminating point, and the nets are made to converge to a wiring starting point taking advantage of a method which converges nets to a virtual point at a step S11. Next, a single broad wiring pattern, which is possessed of a wiring width and a wiring pattern determined basing on currents which flow through the actual wirings of the net between a wiring starting point and a wiring terminating point and a previously determined space between the wirings, is automatically laid. Then, the broad wiring pattern is converted into the wiring pattern of the net, and the wiring pattern of the net located at a corner is replaced with a wiring pattern provided with a via-contact to form a mask data.
申请公布号 JPH06349947(A) 申请公布日期 1994.12.22
申请号 JP19930142347 申请日期 1993.06.14
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 MURAKAMI TAKAKO;TSUYUKI TERUHISA;KAWAZOE KAZUNORI;SHIMAZAKI TAKESHI;NISHIWAKI YUKIMI
分类号 G03F1/00;G06F17/50;H01L21/82 主分类号 G03F1/00
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