| 摘要 |
PURPOSE:To virtually construct an input/output device in a target system and improve the processing speed by providing a connection program which analyzes interruptions and instruction words and receives and passes data in synchronism with operation to the address of the input/output device. CONSTITUTION:When a central processing unit 1 equipped with an interruption input terminal performs reading/writing operation to the address of the input/ output device set in an address specification register 2 while executing a target program 10 to be debugged, a comparator 3 generates an interruption request and the central arithmetic processor 1 interrupts the execution of the target program 10 and the processing is branched to the connection program 11. The final instruction of the interruption request is analyzed and when the connection program 11 is a write instruction, the value of the operand corresponding to the value of an address latch register 4 is passed to the input/output simulator 31. When the connection program is a read instruction, on the other hand, the value from the input/output simulator 4 is substituted in the corresponding destination operand after the value of the source operand is passed. |
