| 摘要 |
A Virus Resilient Processor (VRP) is obtained with use of a "Diverse Instruction Set Architecture" (DISA) comprising an assignment of differing sets of instruction codes (i.e., "opcodes" or operation codes) to different individual processors. In accordance with certain illustrative embodiments of the present invention, an individual "key" associated with a given processor is advantageously used to transform the set of instruction codes to (and from) a particular instruction set. And in accordance with one of these illustrative embodiments of the invention, the set of instruction codes is transformed by permuting (i.e., reordering) the bits of the instruction code in a specific manner based on the individual key. In this manner, since instruction code sets will be diverse across different processors, malicious code can be advantageously thwarted because an attacker will not know the mapping of opcodes to functionality.
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