| 摘要 |
<p>A universal sequential logic circuit is constructed from a rectilinear array of elementary logic circuit 'cells' (102), with a relatively large number of logic states embodied in a relatively small array. A rectilinear array (102) comprises a set of rows (104a) and columns (104b) of logic cells (106). Diagonal logic cells (106) are memory cells (108), while non-diagonal logic cells (106) are function cells (110). Each memory cell (108) stores one bit of state information, and each logic cell (106) is electrically connected to each of its neighbor logic cells (106), for transmitting bits of state information. The set of states from a state-machine description of the logic function desired to be performed is compiled into a software association of cellular array states with each state-machine state, and the set of transitions from the state-machine description is compiled into a software association of logical connections between cells from input line (112). The cellular array performs the state-machine function under software control.</p> |
