发明名称 |
Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank |
摘要 |
A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access request need not wait for a previous access request to be finished. Accordingly, the throughput of the system can be improved greatly.
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申请公布号 |
US5375215(A) |
申请公布日期 |
1994.12.20 |
申请号 |
US19910784546 |
申请日期 |
1991.10.29 |
申请人 |
HITACHI, LTD. |
发明人 |
HANAWA, MAKOTO;NISHIMUKAI, TADAHIKO;NISHII, OSAMU;SUZUKI, MAKOTO |
分类号 |
G06F15/16;G06F12/00;G06F12/06;G06F13/16;G06F15/167;G06F15/177;(IPC1-7):G06F13/36;G06F9/40 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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