| 摘要 |
PURPOSE:To perform the pull-in of a PLL to a correct phase-locked state without being disturbed by a spurious component by performing such control that a specific pattern inserted to an input digital signal in the pull-in process of the PLL is detected and the frequency of a reproducing clock signal can coincide with that of a targeted synchronous clock from a detected pulse. CONSTITUTION:The PLL 10 which performs the phase-lock of a digital input signal to which the specific pattern is inserted at every constant interval with the reproducing signal, and a pull-in control circuit 20 which performs the pull-in of the PLL circuit 10 to the correct phase-locked state are provided. The pull-in control circuit 20 is comprised of a circuit 21 which detects the specific pattern inserted to the input digital signal and generates a specific pattern detection pulse, and a circuit 2 which compares the frequency of the specific pattern detection pulse with that of the reproducing clock signal by conforming to the insertion interval of the specific pattern, and controls the frequency of the reproducing signal so as to be the one of integer times the frequency of the specific pattern detection pulse. |
