发明名称 Protection devices for precision mixed-signal electronic circuits and methods of forming the same
摘要 Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.
申请公布号 US9362265(B2) 申请公布日期 2016.06.07
申请号 US201514593477 申请日期 2015.01.09
申请人 ANALOG DEVICES, INC. 发明人 Salcedo Javier Alejandro;Parthasarathy Srivatsan
分类号 H01L23/62;H01L27/02;H01L21/8222 主分类号 H01L23/62
代理机构 Knobbe Martens Olson & Bear LLP 代理人 Knobbe Martens Olson & Bear LLP
主权项 1. A protection device for a mixed-signal integrated circuit, the protection device comprising: a semiconductor substrate; a first n-type well in the semiconductor substrate; a first p-type well in the semiconductor substrate adjacent the first n-type well; a first n-type active region disposed along a boundary of the first n-type well and the first p-type well; a second n-type active region in the first p-type well; a first p-type active region in the first n-type well; a gate structure over the first n-type well, wherein the first p-type active region is disposed on a first side of the gate structure, and wherein the first n-type active region is disposed on a second side of the gate structure opposite the first side; a second p-type well in the semiconductor substrate, wherein the first n-type well is positioned between the first p-type well and the second p-type well; and an n-type isolation layer beneath the first p-type well, the first n-type well, and the second p-type well.
地址 Norwood MA US