| 摘要 |
PURPOSE:To provide a logic simulation network list which realizes timing simulation of high precision where the effect of inter-wiring capacitive coupling is taken into consideration. CONSTITUTION:Delay adding means 6 and 15 are inserted to node connections 7 and 13 having capacitive coupling 8 in the logic simulation network list. Outputs of logic cell libraries 5 and 14 which drive the capacitive coupling 8 are connected to delay adding means 6 and 15 by capacity virtual connections 11 and 12. Thus, timing simulation of high precision is realized and the margin for timing design can be reduced, and the number of gates, the area, the power consumption, and the cost are reduced. |
