| 摘要 |
<p>PURPOSE:To reduce the probability of synchronization error and to excellently reproduce a synchronizing signal by providing each circuit generating a synchronizing signal by respectively detecting the matching with a fixed data pattern for the output where each bit shift is performed for the output of a delay circuit according to the detection result of the phase matching with the fixed data pattern. CONSTITUTION:Digital data(Dd) delayed by a time interval unit by delay circuits 21 to 25 is delayed by a bit unit by a bit shift detection circuit 26. According to the result where the circuit 6 detects the phase which matches with a fixed data pattern(Dp), variable shift registers VSR 27 to 31 perform each bit for the output Dd of the circuits 21 to 25. As for these shift data SD 0 to 4, synchronizing/ID detection circuits 32 to 36 detect the matching with Dp. According to this result, comparators 37 to 40, a synchronizing location, bit shift correction circuits 41 and 42 and inertia mask circuits 13 and 14 form a synchronizing signal. Thus, the correct synchronizing signal is outputted, and excellently reproduced with low synchronization error rate.</p> |
