| 摘要 |
PURPOSE:To enable a microcomputer system to operate in a normal state after a temporary fault is restored by supplying an abnormality signal to a watch dog timer at the time of the abnormality detection of a memory, and repeatedly resetting a CPU. CONSTITUTION:A CPU 3' operates the abnormality check of a ROM 5 in a time T1 section after an ignition switch 2 is turned on, and operates the abnormality check of a RAM 4 in a following time T2 section. At the time of judging the presence of the abnormality as the result of the abnormality check, a watch dog timer 8' outputs a reset signal, and initializes the CPU 3'. Then, the CPU 3' operates the abnormality check similar to the previous time in a time T3 section following the time T2 section, and in a time T4 section following the time T3 section. Thus, at the time of the temporary abnormality which can be restored, a normal state can be automatically recovered while the ignition switch is turned on as it is, so that reliability on the system can be improved. |
