Basic cell for a channelless gate array device.

摘要

The invention relates to a basic cell for a channelless gate array device ("sea of gate" (SOG) array) produced by a combined CMOS and bipolar technology, each basic cell comprising at least one bipolar transistor and a plurality of metal-oxide field-effect transistors (MOSFET), whose gate electrodes each have two terminal regions which are situated on opposite sides of the associated source-drain region. According to the invention, a bipolar transistor and MOS field-effect transistors of the first and second channel type are situated in a central region of the basic cell, three rows consisting of a plurality of MOS field-effect transistors aligned parallel to one another being provided in each case on opposite sides of said central region. At the same time, the first row in each case consists of oxide-insulated MOS field-effect transistors of the first channel type, the second row consists in each case of gate-insulated MOS field-effect transistors of the first channel type and the third row in each case consists of MOS field-effect transistors of the second channel type, which are also gate-insulated. Furthermore, the two terminal regions of the gate electrodes of the MOS field-effect transistors of the first, second and third rows are in each case mutually offset in relation to the orientation perpendicular to the direction of the rows, the gate electrodes with their terminal regions of the MOS field-effect transistors belonging to a row being aligned parallel to one another. A gate array built up with such a basic cell according to the invention has a high interconnection capability and a high transmission capability, and such a structure makes it possible to design both static and dynamic logic components and also memories such as RAMs and ROMs and input and output driver stages.