| 摘要 |
<p>PURPOSE:To provide a timing reproduction circuit which can realize a stable operation in a wide clock frequency range. CONSTITUTION:A signal delay means VCD to which a clock signal is inputted and to which plural delay elements delaying the clock signal are serially connected, clock output terminals CK1-CKN fetching the output of the signal delay means and a pulse generation order detection means POD monitoring the inverted order of outputs from the respective stages of the delay means are provided. Then, the pulse generation order detection means POD detects whether the output of the delay means in a forefront stage is inverted to same polarity again after the outputs of the delay means in the whole stages of the signal delay means VCD are inverted to one polarity. Thus, an inconvenience that a feedback loop is stabilized by a condition except for a condition that original delay time tau= the period T of the clock signal is prevented and an allowable degree against the variance of the elements generated in a semiconductor integrated circuit is enlarged.</p> |
