摘要 |
<p>PURPOSE: To use DRAM memory and to unnecessitate addition of a refresh control circuit by selecting write or read data in memory and supplying it to an adder by a control signal from a timing control means. CONSTITUTION: A digital signal. which is corrected on time base from a TBC 20 is supplied to an adder 40 and a data selection part 34. The selection part 34 writes or reads 1st and 2nd frame memory 31 and 32 according to a control signal from a timing block 33. When the memory 31 writes, the memory 32 reads, and the selection part 34 writes and reads the memory 31 and 32. At this time, the block 33 supplies a low address strobe signal RAS, a column address strobe signal CAS and an address signal ADDR to the memory 31 and 32 and accesses addresses in the memory. Thereby, even when an inexpensive DRAM memory is used, a refresh control circuit has not to be added and a system is simplified.</p> |