Semiconductor memory device providing reduced test time

摘要

In a memory cell array having a plurality of memory cells connected to store physical information levels different in adjoining pairs of complementary data lines, those pairs of the memory cells, with which are connected the memory cells for storing the physical information levels in an identical pattern, are connected with a plurality of input/output lines by a column select circuit, so that the plurality of memory cells may be caused to perform the writing operations simultaneously in a test mode by feeding an identical write signal to the plurality of input/output lines. In the test mode, moreover, the input write data are processed so that the physical information levels of adjoining memory cells to be simultaneously written in the plurality of memory cells may be coincident. Since the information levels of the adjoining bits can be made physically identical or different by combining the address selection and the write data, it is possible to shorten the testing time.