发明名称 TEST CIRCUIT FOR SEMICONDUCTOR MEMORY
摘要 PURPOSE: To provide two current detection differential amplifiers together with a testing circuit for testing entire rows along one word line and to simultaneously test entire rows of memory array without adding a sense amplifier. CONSTITUTION: When every cell correctly stores logic 1, current does not flow to a teat line TL, and the current which is equal to a product acquired from current derived by a single memory cell and the number of accessed memory cells flows to a complementary test line TLB. When current does not exist in the line TL, an output of a 1st differential amplifier 10 becomes low, and when current exists in the line TLB, an output of a 2nd differential amplifier 12 becomes high. A comparator 14 detects two opposite logic states of logical value of the test amplifiers 10 and 12 and outputs value of the logic 1 which shows that appropriate data is stored in memory cell. This means that the test result for entire memory cells along the word line is satisfactory.
申请公布号 JPH06318400(A) 申请公布日期 1994.11.15
申请号 JP19930223679 申请日期 1993.09.08
申请人 SONY ELECTRON INC 发明人 RII RIAN SHIYUU;KAATO NOOPU;SENOO KATSUNORI
分类号 G01R31/28;G11C11/413;G11C29/34;G11C29/38;(IPC1-7):G11C29/00;G01R31/318 主分类号 G01R31/28
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