| 摘要 |
PURPOSE:To prevent the decrease in working speed of the titled device by a method wherein, in the case of the LSI or VLSI of master slice system, the wiring between fundamental cells is formed using a low resistance wiring material. CONSTITUTION:In the LSI or VLSI of master slice where a fundamental cell is formed using a CMOS, the fundamental cell 3 to be formed on a semiconductor substrate has an N type region 7, a P type region 8 and gate electrodes 9, 10 and 11 formed in Y-direction with a polycrystalline silicon. Wirings 14, 15, 18, 19 and 20 are formed in X-direction as the second layer on the gate electrodes 9, 10 and 11 using the low resistance material such as aluminum and the like through the intermediary of an interlayer insulating film. The wiring 14 is connected to the source voltage, and the wiring 15 is grounded, and the wirings 18, 19 and 20 are provided for the purpose of transmission of the signal between fundamental cells. A wiring 21 is formed in Y-direction on the wirings 14, 15, 18, 19 and 20 as the third layer using a low resistance material through the intermediary of an interlayer insulating film, and it is connected to the gate electrode 9 and the wirings 19 and 20 using a through hole. |
