| 摘要 |
A bus interface for connecting two busses. It includes a first and second bus interface circuitry, central buffer and control circuitry. The control circuitry includes two control sequence circuitry for tracking and controlling the channels of data within a FIFO device. The sequence control circuitry includes a circular queue for providing a predetermined number of slots, each slot capable of containing the identity and the status of the channel of data already resident in the FIFO device, and capable of containing the identity of the channel of data pending residence in the FIFO device. The sequence control circuitry further includes two pointers for traversing the circular queue, slot by slot. The first pointer checks if the slot contains the identity of a resident channel, if so it updates the status information in the slot, and if the slot does not contain the identity of a resident channel, then determines whether any channels are pending residence in the FIFO device, and if so inserting the identity of the pending channel and commencing transfer of the pending channel into the FIFO device if there is enough room. The second pointer checks to see if a slot contains the identity of a FIFO device resident channel, if so it then commences transfer of that channel from the FIFO device. The pointers are prevented from advancing to the same slot so that resident channels of data in the FIFO device are not overwritten before the resident channels of data are outputted from the FIFO device
|
