| 摘要 |
<p>PURPOSE:To prevent a device mounted with a CPU from performing wrong operation even when a reset signal arrives optionally. CONSTITUTION:An inhibition signal generating means 7 outputs a significant inhibition signal while the CPU 1 performs operation wherein the rejection of the input of the reset signal is desirable. When a reset signal generating means 2 generates the reset signal while the inhibition signal is significant, a reset signal inhibiting means 3 inhibits the reset signal from being inputted to the CPU. Here, a reset signal delay means 4 and delay reset signal input means 5 and 6 are further provided and it is preferable that the reset signal delay means delays the generated reset signal throughout the execution of the operation by the CPU wherein the rejection of the input of the reset signal is desirable and the delay reset signal input means input the delayed reset signal to the CPU at the end of the operation by the CPU.</p> |
