| 摘要 |
PURPOSE:To accelerate an operation of an LSI by reducing the signal delay due to a parasitic CR of a signal line having a long length when a plurality of signal lines having different lengths are aligned in parallel in an LSI chip. CONSTITUTION:When a plurality of signal lines A0-A5 having different lengths are aligned in parallel with each other in an LSI chip lines are wired, either by setting intervals of the lines to be equal and the signal line width is reduced sequentially from longer line A0 toward shorter line A5, or the widths of the lines are set equal and the intervals of the lines are narrowed sequentially from the longer line A0 toward the shorter line A5, or the width is sequentially reduced from the longer line A0 toward the A5 and simultaneously the intervals of the lines are sequentially narrowed. Thus, signal delay differences between the lines are reduced to accelerate the operation of the LSI. |
