COMPOSITE CLOCK SIGNAL

摘要

The present invention provides a composite clock signal, CLSY, which with one single signal distributes both clock signal and synchronizing signal, wherein the detection of this synchronizing signal in a subsequent bit clocking generator for a high bit clocking frequency (fBCL) means that any time jitter that may exist on the edges of the clock signal (CLSY) will not influence the definition of the locally obtained synchronizing signal (SYN1), wherein each data bit frame defined by the synchronizing signal (SYN1) will always include the exact number of data bits at the bit clocking frequency (fBCL). The bit clocking generator includes basically a PLL-circuit, a dividing circuit and a shift register and a logic gate for generating from the CLSY-signal the bit clocking signal with its frame reference, wherein there is obtained from the bit clocking generator in addition to the bit clocking frequency a synchronizing pulse which has high precision in relation to both the high frequency system clock and also in relation to an external time domain transferred through the composite reference signal (CLSY).