发明名称
摘要 PURPOSE:To improve the degree of integration of an EPROM, and to enhance the efficiency of writing by forming a semiconductor region in a LDD section in a FET for a memory cell in the EPROM in impurity concentration higher than the LDD structure of a FET for a peripheral circuit. CONSTITUTION:An X decoder 1 selects a predetermined word line, and turns a prescribed memory ON. A Y decoder 2 selects a predetermined decoder line, and applies voltage as informations. Writing circuits 3, 3' write informations to prescribed memory cells. A sense amplifier 4 reads the informations of predetermined memory cells. These elements constitute a peripheral circuit for an EPROM. Word lines WL1...WLm are connected to the X decoder 1 and the writing circuit 3. Data lines DL1...DLm are connected to the Y decoder 2, the writing circuit 3' and the sense amplifier 4. A plurality of memory cells M11, M12... Mnm are arranged and formed at prescribed crossed sections among the word lines WLs and the data lines DLs, and connected to FETs, one ends thereof are grounded, and constitute the informations of the EPROM.
申请公布号 JPH0685442(B2) 申请公布日期 1994.10.26
申请号 JP19840102555 申请日期 1984.05.23
申请人 HITACHI LTD 发明人 KOMORI KAZUHIRO;KURODA KENICHI;SUGIURA JUN
分类号 H01L21/28;H01L21/8247;H01L27/105;H01L29/788;H01L29/792;(IPC1-7):H01L29/788 主分类号 H01L21/28
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