LAY-OUT METHOD OF INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE,申请号JP19930080904-传众专利搜索

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发明名称	LAY-OUT METHOD OF INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
摘要
申请公布号	JPH06295955(A)	申请公布日期	1994.10.21
申请号	JP19930080904	申请日期	1993.04.07
申请人	SEIKO EPSON CORP	发明人	SUGANUMA TATSUJI
分类号	H01L21/82;G06F17/50;H01L21/822;H01L27/04;(IPC1-7):H01L21/82;G06F15/60	主分类号	H01L21/82
代理机构		代理人
主权项
地址

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