Electrically erasable non-volatile semiconductor memory device.

摘要

In an electrically erasable non-volatile semiconductor memory device, a plurality of non-volatile semiconductor memory cells (TMll SIMILAR TMmn) are arranged in a matrix from and are connected to corresponding ones of row and column lines (Rl SIMILAR Rm, Dl SIMILAR Dn). In a data writing mode, a first voltage Vp is applied to the column lines (Dl SIMILAR Dn) so that the drains of the memory cells (TMll SIMILAR TMmn) are maintained at a drain potential, and a second voltage is applied to the row lines (Rl SIMILAR Rm) so that a sum level of the drain potential and the threshold voltage of the memory cell (TMll SIMILAR TMmn) is not smaller than the floating gate potential of the memory cell (TMll SIMILAR TMmn).