| 摘要 |
PURPOSE:To improve frequency characteristics by limiting a current flowing between power supplies, by interposing impedance between the substrate of an integrated circuit and the source of FET. CONSTITUTION:Between positive power supply potential VDD and 2nd negative power supply potential VSS2 with a potential to be level-shifted, resistance R1, P channel FETT5, N channel FETT6, and resistance R2 are connected in series and capacitor C3 is connected at one side to the connection point of drains of FETs T5 and T6 and to the output of inverter INV2 at the other side. In addition, input terminal CLK is connected to the input terminal of INV2 and gates of FETs T5 and T6 at the same time, and the connection point of drains of FETs T5 and T6 is to output terminal OUT2. The positive power supply of INV2 is connected to VDD and 1st negative power supply potential VSS1 is to the negative power supply. |
