发明名称 SIGNAL PROCESSOR
摘要 PURPOSE:To improve the arithmetic efficiency and to easily estimate the number of arithmetic steps. CONSTITUTION:An absolute value conversion part 14, a multiplier 18, and a product sum unit 34 processes IN and TMP from a memory 10 and coefficients 1.0 and -1.0 from a memory 20 to obtain ABS(IN)-TMP. A sign judgement part 26 judges whether it is plus or minus and controls a mask part 24. When the result is plus, a multiplier 18 multiplies the absolute value ABS(IN) of IN by the coefficient 1.0 and the result is stored in the product sum unit 34. The TMP is supplied to the multiplier 18 and the coefficient 1.0 of a memory 20 is masked by the mask part 24 and supplied to the multiplier 18. Its multiplication result 0 and the ABS(IN) of the product sum unit 34 are added to obtain a sum ABS(IN). When the result is minus, on the other hand, the value of the product sum unit 34 is regarded as TMP as mentioned above. Then, -DEC is read out of the memory 20 and supplied to the multiplier 18 without being masked by the mask part 24. At the same time, 1 is supplied from a bit set part 16 to the multiplier 18, whose multiplication result is -DEC. This is added to the TMP by the product sum unit 34 to obtain TMP-DEC.
申请公布号 JPH06290202(A) 申请公布日期 1994.10.18
申请号 JP19930098818 申请日期 1993.03.31
申请人 ROLAND CORP 发明人 NOZAWA NAOYA
分类号 G10H1/00;G06F17/10 主分类号 G10H1/00
代理机构 代理人
主权项
地址