发明名称 PLL CIRCUIT
摘要 PURPOSE:To provide the PLL circuit equipped with optimum convergent characteristics and frequency stability by changing convergent speed while depending on the characteristic of a low-pass filter(LPF) to change a cut-off frequency or the like based on a prescribed voltage supplied from a frequency/ voltage conversion part. CONSTITUTION:A phase comparator 1 detects phase difference between an input signal 10 and a feedback signal 12 and outputs a signal corresponding to phase difference to an LPF 2. A VCO 3 is controlled by a DC voltage from the LPF 2 and generates a prescribed clock output signal 11 based on a frequency selection signal 15. A frequency divider 4 divides the frequency of the signal 11 and changes a frequency dividing ratio based on the signal 15, and a frequency/voltage converting part (F/V) 5 inputs the signal 11 and outputs a voltage 16 corresponding to the frequency. As a result, the F/V 5 supplies the prescribed voltage signal 16 to the LPF 2 corresponding to the frequency of the output signal 11, namely, the oscillation frequency. The LPF 2 changes the transmission characteristic such as the cut-off frequency and as a result, the PLL circuit changes loop sensitivity and shortens the convergent time of frequency lock.
申请公布号 JPH06291654(A) 申请公布日期 1994.10.18
申请号 JP19930080385 申请日期 1993.04.07
申请人 FUJITSU GENERAL LTD 发明人 MATSUURA SHOJI
分类号 H03L7/093;H03L7/08;H03L7/107 主分类号 H03L7/093
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