发明名称 FLOATING POINT ARITHMETIC UNIT
摘要 PURPOSE:To solve a trouble of performance drop to be generated when an interruption report is delayed by quickly detecting the operation exceptions of an exponent overflow and an exponent underflow by a floating point multiplying instruction and informing an interruption. CONSTITUTION:An operation exception detecting part 200 consists of a post- multiplication normalized quantity detecting circuit 201, a post-multiplication exponent calculating circuit 202, an exponent underflow detecting circuit 203, an exponent overflow detecting circuit 204, an AND gate 205, etc., and constituted so that the normalized quantity of the multiplied result of a multiplicand and a multiplier is found out by the circuit 201, the exponent of the multiplied result is fount out by the circuit 202 and an exponent overflow and an exponent underflow are quickly detected respectively by the circuits 203, 204 based on the exponent of the multiplied result.
申请公布号 JPH06290023(A) 申请公布日期 1994.10.18
申请号 JP19930075632 申请日期 1993.04.01
申请人 HITACHI LTD;HITACHI COMPUT ENG CORP LTD 发明人 TAKIGUCHI MAKOTO
分类号 G06F7/00;G06F7/487;G06F7/52;G06F7/76 主分类号 G06F7/00
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