发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To use the output result of a multiplier as an input to the multiplier immediately in a next machine cycle. CONSTITUTION:In the arithmetic unit which performs data transfer, multiplication, and ALU arithmetic by a pipeline system by cascading the multiplier 1 having two input and output latches 4 and a data ALU circuit 5 having two inputs, the output latch 4 of the multiplier 1 is connected to a selector 7 for one input of the data ALU circuit 5 and also connected to selectors 2 and 3 for two inputs of the multiplier 1, and a register file 8 and the output latch 4 of the multiplier 1 can be selected as the input to the multiplier 1. Then when continuous arithmetic processing for a three-term product, a four-term product, a five-term product, etc., is performed, the output of the output latch 4 can be supplied directly to the input of the multiplier 1 through the selectors 2 and 3 and the number of execution steps can greatly be decreased.
申请公布号 JPH06282418(A) 申请公布日期 1994.10.07
申请号 JP19930071326 申请日期 1993.03.30
申请人 N T T IDOU TSUUSHINMOU KK 发明人 MIKI YOSHINORI;MIKI TOSHIO;OYA TOMOYUKI;OKUMURA YUKIHIKO
分类号 G06F7/53;G06F7/52;G06F7/523 主分类号 G06F7/53
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