| 摘要 |
PURPOSE:To obtain the multiplier which suppresses layout area and enables high-speed processing. CONSTITUTION:In a partial product addition part 45, 6-2 Wallace parts 1-3, a parallel carry saving adder 5, a 6-2 Wallace part 4, and a parallel carry saving adder 6 are arranged in order from the above position and a partial product of multiplier data Y and a multiplicand X is generated by using a secondary booth and compressed to two bits respectively by the 6-2 Wallace parts 1-4. The compression results are propagated by the parallel carry saving adders 5 and 6. Consequently, the compression results are propagated by the parallel carry saving adders by using the 6-2 Wallace parts which are fast, but relatively small to decrease the number of electric conductors and reduce the area and shorten the multiplication time. |
