Circuit controlling HS-NMOS power switches with slew-rate limitation

摘要

The present document relates to NMOS switches. In particular, the present document relates to a method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches. A circuit arrangement configured to control a first NMOS switch is described. The arrangement (120) comprises voltage provisioning means (121) configured to supply a gate voltage to a gate terminal (102) of the first NMOS switch (100); current provisioning means (121) configured to provide a current; a first control stage (130) configured to provide and/or remove a connection between the gate terminal (102) of the first NMOS switch (100) and the voltage provisioning means (121), thereby switching the first NMOS switch (100) to an on-state and/or an off-state, respectively; and a first feedback control link (122, 140) between an output terminal (103) of the first NMOS switch (100) and the current provisioning means (121) configured to control the slew-rate of a voltage at the first output terminal (102).