| 摘要 |
<p>PURPOSE:To enable bulk transfer by adding the external input/output terminals of a circuit for two-channel bulk transfer use and a register, cascade-connecting them and specifying as 64kbpsX(n) ((n) is an integer of >=2.) CONSTITUTION:This device is provided with interface circuits 15, 18, ..., provided with the layer 1 function of an ISDN (integrated services digital network) circuit, bulk transfer circuits for performing the delay correction of data corresponding to control signals and memories 17, 20, ..., for storing the data to be corrected in delay. Also, cascade connected plural correction circuits 11, 12, ... 13 and the function of the layers 2 and 3 of the ISDN circuit are provided and a control circuit CPU 14 for supplying the control signals simultaneously to the respective correction circuits is provided. In such a manner, by cascade- connecting the control circuit CPU 14, the delay correction of a B channel >=2B is enabled and the data transfer of 64kbpsX(n) ((n is the integer of >=2) >=125kbps can be executed.</p> |
