| 摘要 |
PURPOSE:To switch a self-run mode by detecting a break of an input synchronizing signal logically in a PLL circuit. CONSTITUTION:The PLL circuit consisting of a D/A converter 4, a phase comparator 7 which compares a saw-tooth wave as its output with the input synchronizing signal 12, a voltage-controlled oscillator 1, and a counter 2 a self-run/ synchronism deciding circuit which counts the frequency of the saw-tooth wave and outputs a synchronism/self-run decision signal 15 by having a decoder decoded with the output of a counter having (n) bits added on its MSB side and an RS flip-flop 8 which is set with the decoder output to sets the input synchronizing signal 12. Consequently, the need to incorporate a large-capacity capacitor is eliminated and the chip size is reducible. Further, this circuit is applicable to any frequency range without complicated circuit design. |
