| 摘要 |
A memory cell comprising two assemblies each including first to third transistors (MP1, MN5, MN1; MP2, MN6, MN2) arranged between high and low potentials (Vdd, Vss). The first transistor (MP1, MP2) is a p-channel transistor while the second and third are n-channel transistors. The gate of the third transistor in each assembly is connected to the output node of the other assembly while the gate of the second transistor in each assembly is connected to the gate of the first transistor in the other assembly. A fourth p-channel transistor (MP3, MP4) combined with each assembly is arranged between the high potential (Vdd) and the gate of the first transistor (MP1, MP2) in the assembly. A fifth n-channel transistor (MN7, MN8) combined with each assembly is arranged between the gate of the first transistor in the assembly and the low potential (Vss). |
