| 摘要 |
PURPOSE:To easily change a delay time between an input signal and an output clock by inputting an input signal of the PLL circuit and the output of an analog delay device using a D flip-flop for its pre-stage circuit. CONSTITUTION:The output of a phase comparator 4 is inputted to a low pass filter 5. The DC output of the low pass filter 5 is inputted to a voltage controlled oscillator 6, whose output clock 3 is used for the system of a next stage. Moreover, the output clock 3 is inputted to a 1/M frequency divider 7, and an output signal 2 subjected to 1/M frequency division is used for a system of a next stage as an output signal of a PLL (phase locked loop) circuit. On the other hand, the output signal 2 is inputted to an analog delay device 10 to delay the output clock 3 for an optional time with respect to the input signal 1 of the PLL circuit. Thus, the delay quantity of the analog delay device 10 is halved in comparison with that of a conventional circuit to half the number of components such as taps used for selecting a delay time thereby reducing the dispersion in the delay time. |
