| 摘要 |
An address control system for a RAM, comprising a synchronous counter for receiving input data according to a clock signal and providing n-bit row column address, and an n-bit column address a first buffer for receiving the n-bit row address from the synchronous counter and generating the n-bit row address, a first tri-state inverter for outputting data stored in a ROM according to a write enable signal a second tri-state inverter for outputting reference data according to the write enable signal, an adder for adding the n-bit column address from the synchronous counter and output address signals from the first inverter, and a second buffer for receiving output signals from the adder generating a column address delayed from the n-bit column address. |
