发明名称 |
MASK-PROGRAMMED INTEGRATED CIRCUITS HAVING TIMING AND LOGIC COMPATIBILITY TO USER-CONFIGURED LOGIC ARRAYS |
摘要 |
Method and apparatus for producing mask-configured integrated circuits which are pin, logic, and timing compatible substitutes for user-configured logic arrays (10), without the need for logic or timing simulations of the mask-configured circuit design. Scan testing networks of test blocks and modified flip-flops are included in the mask-configured substitutes to test functionality. Logic compatibility to the user-configured logic array (an FPGA) (10) is preserved by clustering together in the mask-configured integrated circuit (a gate array) (16) all of the logic gates which perform the functions of a particular FPGA logic block. Moreover, only those FPGA logic gates or functions which are used are replicated in the gate array, to conserve chip area. |
申请公布号 |
WO9420909(A1) |
申请公布日期 |
1994.09.15 |
申请号 |
WO1994US02398 |
申请日期 |
1994.03.11 |
申请人 |
XILINX, INC. |
发明人 |
BUCH, KIRAN, B.;LAW, EDWIN, S.;CHU, JAKONG, J. |
分类号 |
G06F11/22;G01R31/3185;G06F11/26;G06F17/50;H01L21/82;(IPC1-7):G06F15/20;H04B17/00 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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