发明名称 |
Static ram cell with trench pull-down transistors and buried-layer ground plate. |
摘要 |
<p>Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned poly-silicon p-channel pull-up transistors without appreciably enlarging the cell area.</p> |
申请公布号 |
EP0297350(B1) |
申请公布日期 |
1994.09.07 |
申请号 |
EP19880109475 |
申请日期 |
1988.06.14 |
申请人 |
INTEGRATED DEVICE TECHNOLOGY, INC. |
发明人 |
HSU, FU-CHIEH |
分类号 |
H01L21/74;H01L21/8244;H01L23/532;H01L27/11;H01L29/78;(IPC1-7):H01L27/11 |
主分类号 |
H01L21/74 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|