发明名称 |
Visual frame buffer architecture |
摘要 |
An apparatus for processing visual data includes a first video random access memory (VRAM) for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first VRAM by a data bus and a storage bus. The apparatus is capable of receiving at least a second VRAM for storing at least a second bit plane of visual data in at least a second format different from the first format. The received VRAMs are coupled to the graphics controller by data and storage busses. The visual data stored on the VRAMs are merged into a pixel stream which is then converted to analog form by a digital to analog converter. Data transfer addresses are generated for each of the VRAMs simultaneously, sequentially or in overlapping timed relationship.
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申请公布号 |
US5345554(A) |
申请公布日期 |
1994.09.06 |
申请号 |
US19920901434 |
申请日期 |
1992.06.19 |
申请人 |
INTEL CORPORATION |
发明人 |
LIPPINCOTT, LOUIS A.;RUTMAN, SERGE |
分类号 |
H04N5/262;G06F3/153;G09G5/02;G09G5/36;G09G5/39;G09G5/397;G09G5/399;H04N5/445;H04N9/75;(IPC1-7):G06F15/20 |
主分类号 |
H04N5/262 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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