Method of compressing and decompressing simulation data for generating a test program for testing a logic device

摘要

A method for simulating a logic device is described wherein a sequence of input vectors to a computer simulation is reduced in order to save computational time and data storage requirements when the sequence includes a series of redundant input vectors having the same expected output vectors. The method reduces the number of redundant input vectors to be applied to the computer simulation by eliminating all but the first input vector of series while encoding a plurality of control bits associated with that input vector with information indicating the number of redundant input vectors being eliminated. Subsequently, after the simulation of the logic device, the output vectors resulting from the simulation are combined with their respective input vectors to form a set of test vectors. Using the encoded information in the first input vector of the series of redundant input vectors, the thus generated set of test vectors is then expanded to form an expanded set of test vectors suitable for generating a test program for testing the logic device on a logic device tester.