| 摘要 |
A phase locked loop includes a linear phase detector responsive to a first signal having a predetermined range of frequencies and a second signal for comparing the relative phase of the first signal and the second signal, and a loop gain stabilization circuit coupled between the source of the first signal and the linear phase detector for reducing the magnitude of variations in the loop gain of the phase locked loop over the predetermined range of frequencies of the first signal source. An embodiment of the linear phase detector comprises a harmonic sampler/presteer circuit. The construction and operation of the loop gain stabilization circuit depends on whether the phase locked loop is being used in a frequency multiplying or dividing circuit.
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