发明名称 METHOD AND DEVICE FOR CLOCK SYNCHRONIZATION
摘要 <p>PURPOSE:To prevent the deviation of transmission/reception timings generated when a reception electric field level declines by comparing a detected electric field level with a threshold value and outputting a compared result as the changeover signals of clock signals. CONSTITUTION:A reception part 1 smooths an intermediate frequency IF to be defined as the level information of a reception electric field and outputs it to a level comparator circuit 3. The circuit 3 compares the electric field level information outputted from the reception part 1 with the preset threshold value and sends clock changeover signals to a clock synchronization circuit 2 so as to respectively output synchronous clock signals when an electric field level value is higher and free-running clock signals when the threshold value 15 higher. A timing control circuit 5 inputs the clock signals outputted from the circuit 2 and outputs the transmission/reception timing control signals of data to the reception part 1 and a multiplexing/demultiplexing circuit 4. By this constitution, even when the electric field level of reception radio waves declines and the phase of the clock signals is disturbed, the deviation of the timings of the operation of the circuit 4 can be surely prevented.</p>
申请公布号 JPH06244772(A) 申请公布日期 1994.09.02
申请号 JP19930295426 申请日期 1993.11.25
申请人 NEC CORP 发明人 NAKANO FUMIO
分类号 H04B7/26;H04J3/06;H04L7/027;(IPC1-7):H04B7/26 主分类号 H04B7/26
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